1. Field of the Invention
The invention relates to video interface and more particularly, to an apparatus and method for reducing output rate of video data for DisplayPort receiver.
2. Description of the Related Art
FIG. 1 shows a schematic diagram illustrating a DisplayPort interface 130 coupling a source device 110 with a sink device 120, and the data flow through the interface.
DisplayPort is a new digital display interface standard put forth by the Video Electronics Standard Association (VESA). As shown in FIG. 1, the DisplayPort interface 130 consists of a Main Link, an auxiliary channel (AUX CH), and a hot plug detect (HPD) signal line. The auxiliary channel with low-latency (each transaction taking no longer than 500 μs), providing for 1 Mbps of data rate of auxiliary nature, is a half-duplex bidirectional channel used for main link management and device control (upon the source device 110 and the sink device 120). The HPD signal line can serve to issue an interrupt request by the sink device (or receiver) 120 to the source device (or transmitter) 110.
Main Link is a high-bandwidth, low-delay, uni-directional interface for isochronous streaming. The number of lanes of Main Link can be either 1, 2, or 4 lanes, for providing for simultaneous digital video and audio streaming transmission. Each lane supports transmission at two link rates (Flink): 1.62 Gbps or 2.7 Gbps per lane. Therefore, DisplayPort offers up to 10.8 Gbps of bandwidth. It should be noted that in the following description the above-mentioned link rate Flink should be distinguished from another two transmission rates, a link symbol rate Fsym and a pixel rate Fpix. The link symbol rate Fsym indicates the data-transfer rate in terms of symbol over the Main Link. For each lane, eight bits are generally transmitted for each symbol, which means that only a portion of the data of a pixel is transmitted by each symbol, such as the red (R) data in red/green/blue (RGB) pixel data. In practice, the link symbol rate Flink is defined as 1/10 of the link rate Flink through downsampling; therefore two link symbol rate Fsym can be observed: 162 Mbps and 270 Mbps. The pixel rate Fpix, decoupled from the link symbol rate Fsym and the link rate Flink, refers to the pixel (each pixel generally containing 24 bits, i.e., all RGB data) transfer rate of the source device 110.
DisplayPort requires no dedicated channel for forwarding clock. The sink device 120 utilizes data recovery strategy to recover the link symbol rate Fsym from the received data streams. While utilizing the DisplayPort to transmit data, the source device 110 generates the pixel data at a pixel rate Fpix, which is decoupled from the link rate Flink. The source device 110 delivers time stamp values Mvid [23:0], Nvid [23:0] to the sink device 120 by means of frequency ratio packets (the frequency ratio packets also contain the audio time stamp values Maud and Naud, which are not to be discussed herein) or stream attribute packets specified by DisplayPort standard, according to which the sink device 120 is able to recover a pixel clock CLKpix having the pixel rate Fpix. In other words, the sink device 120 can recover the pixel clock CLKpix or the pixel rate Fpix of the transmit device 110 according to the link symbol clock CLKsym (having the link symbol rate Fsym) the time stamp values Mvid, Nvid, and a circuit configuration, as shown in FIG. 2, including two frequency dividers 210, 230 and a phase-locked loop (PLL) 220; that is, the pixel clock CLKpix and the symbol clock CLKsym are decoupled from each other in the source device 110, and the conversion or mapping between these two clocks is conveyed in the time stamp values Mvid, Nvid and expressed as the following mathematical equation: Tpix×Mvid=Tsym×Nvid. Accordingly, the pixel rate can be derived as follows: Fpix=(Mvid/Nvid)×Fsym.
FIG. 3A shows a diagram illustrating relevant image attribute parameters of a frame. FIG. 3B shows a timing diagram illustrating the relationship of a vertical synchronization signal VS, a horizontal synchronization signal HS, and a data enable signal DE. The main stream attribute packet transmitted by the source device 110 further contains the following image attribute parameters (referring to FIG. 3A): a frame width Htotal, a frame height Vtotal, a left blanking width Hstart, a top blanking height Vstart, an active area width Hwidth, an active area height Vheight, a vertical synchronization width WVS, a horizontal synchronization width WHS, and so forth, which are provided for the sink device 120 to recover the original frame format, i.e., both the size and relative location of the active area 310 and the blanking (or non-active) area 320 in a frame.
Compliant with the DisplayPort specification, the sink device 120 utilizes the above-mentioned recovered pixel rate Fpix as the sampling frequency for transmitting the video data to the back-end circuit, and subsequently constructs or recovers image control signals according to the above-mentioned image attribute parameters. Referring to FIG. 3B, firstly, a vertical synchronization signal VS is constructed according to a pixel period Tpix and the vertical synchronizing width WVS (in terms of pixel periods), and then the horizontal synchronizing signal HS is constructed according to the pixel period Tpix, the frame width Htotal, and the horizontal synchronization width WHS (in terms of the pixel periods). Finally, the data enable signal DE and a field signal FIELD (not shown) are constructed according to the pixel period Tpix, the left blanking width Hstart, and the active area width Hwidth, so that the video data can be further processed according thereto.
According to the DisplayPort specification, the sink device 120 is designed only to recover the original pixel clock CLKpix. However, there will be a need for the sink device 120 to reduce the pixel rate Fpix when the back-end circuit includes either components requiring a large amount of computation such as a scaler, or a display monitor having a lower display frequency, or is limited to the physical constraint of printed circuit boards.
To meet this need, on condition that both the data volume and contents of the active area are not affected, the output rate of video data (or pixel rate) needs to be reduced to become compatible with more types of back-end circuits.